A latch circuit operates as a digital sample and hold circuit. It has two inputs, a data input and a clock. Information presented at the data input is transferred to the output when the clock goes high. When the clock goes low, the information that was present at the data input at the time the clock transition occurred is retained at the output. Thus, the trailing edge of the clock samples the data line and the circuit holds (stores) the binary information at the transition. Hence, this circuit is common in many digital circuits and widely used for many applications.
One of the fastest known CMOS latch implementations is a transmission gate latch, but unfortunately this latch design is sensitive to coupled or other forms of noise induced on the data input node. It would be desirable to provide a fast, but noise immune static latch for the purposes for storing digital signals.